avr-libc: power.h Source File

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power.h
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1/* Copyright (c) 2006, 2007, 2008 Eric B. Weddington
2 Copyright (c) 2011 Frédéric Nadeau
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright
9 notice, this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright
11 notice, this list of conditions and the following disclaimer in
12 the documentation and/or other materials provided with the
13 distribution.
14 * Neither the name of the copyright holders nor the names of
15 contributors may be used to endorse or promote products derived
16 from this software without specific prior written permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 POSSIBILITY OF SUCH DAMAGE. */
29
30/* $Id: power.h 2525 2016-09-15 10:24:25Z pitchumani $ */
31
32#ifndef _AVR_POWER_H_
33#define _AVR_POWER_H_ 1
34
35#include <avr/io.h>
36#include <stdint.h>
37
38
39/** \file */
40/** \defgroup avr_power <avr/power.h>: Power Reduction Management
41
42\code #include <avr/power.h>\endcode
43
44Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that
45allow you to reduce power consumption by disabling or enabling various on-board
46peripherals as needed. Some devices have the XTAL Divide Control Register
47(XDIV) which offer similar functionality as System Clock Prescale
48Register (CLKPR).
49
50There are many macros in this header file that provide an easy interface
51to enable or disable on-board peripherals to reduce power. See the table below.
52
53\note Not all AVR devices have a Power Reduction Register (for example
54the ATmega8). On those devices without a Power Reduction Register, the
55power reduction macros are not available..
56
57\note Not all AVR devices contain the same peripherals (for example, the LCD
58interface), or they will be named differently (for example, USART and
59USART0). Please consult your device's datasheet, or the header file, to
60find out which macros are applicable to your device.
61
62\note For device using the XTAL Divide Control Register (XDIV), when prescaler
63is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
64that Timer/Counter0 source shall be less than ¼th of peripheral clock.
65Therefore, when using a typical 32.768 kHz crystal, one shall not scale
66the clock below 131.072 kHz.
67
68*/
69
70
71/** \addtogroup avr_power
72
73\anchor avr_powermacros
74<small>
75<center>
76<table border="3">
77 <tr>
78 <td width="10%"><strong>Power Macro</strong></td>
79 <td width="15%"><strong>Description</strong></td>
80 </tr>
81
82 <tr>
83 <td>power_aca_disable()</td>
84 <td>Disable the Analog Comparator on PortA.</td>
85 </tr>
86
87 <tr>
88 <td>power_aca_enable()</td>
89 <td>Enable the Analog Comparator on PortA.</td>
90 </tr>
91
92 <tr>
93 <td>power_adc_enable()</td>
94 <td>Enable the Analog to Digital Converter module.</td>
95 </tr>
96
97 <tr>
98 <td>power_adc_disable()</td>
99 <td>Disable the Analog to Digital Converter module.</td>
100 </tr>
101
102 <tr>
103 <td>power_adca_disable()</td>
104 <td>Disable the Analog to Digital Converter module on PortA</td>
105 </tr>
106
107 <tr>
108 <td>power_adca_enable()</td>
109 <td>Enable the Analog to Digital Converter module on PortA</td>
110 </tr>
111
112 <tr>
113 <td>power_evsys_disable()</td>
114 <td>Disable the EVSYS module</td>
115 </tr>
116
117 <tr>
118 <td>power_evsys_enable()</td>
119 <td>Enable the EVSYS module</td>
120 </tr>
121
122 <tr>
123 <td>power_hiresc_disable()</td>
124 <td>Disable the HIRES module on PortC</td>
125 </tr>
126
127 <tr>
128 <td>power_hiresc_enable()</td>
129 <td>Enable the HIRES module on PortC</td>
130 </tr>
131
132 <tr>
133 <td>power_lcd_enable()</td>
134 <td>Enable the LCD module.</td>
135 </tr>
136
137 <tr>
138 <td>power_lcd_disable().</td>
139 <td>Disable the LCD module.</td>
140 </tr>
141
142 <tr>
143 <td>power_pga_enable()</td>
144 <td>Enable the Programmable Gain Amplifier module.</td>
145 </tr>
146
147 <tr>
148 <td>power_pga_disable()</td>
149 <td>Disable the Programmable Gain Amplifier module.</td>
150 </tr>
151
152 <tr>
153 <td>power_pscr_enable()</td>
154 <td>Enable the Reduced Power Stage Controller module.</td>
155 </tr>
156
157 <tr>
158 <td>power_pscr_disable()</td>
159 <td>Disable the Reduced Power Stage Controller module.</td>
160 </tr>
161
162 <tr>
163 <td>power_psc0_enable()</td>
164 <td>Enable the Power Stage Controller 0 module.</td>
165 </tr>
166
167 <tr>
168 <td>power_psc0_disable()</td>
169 <td>Disable the Power Stage Controller 0 module.</td>
170 </tr>
171
172 <tr>
173 <td>power_psc1_enable()</td>
174 <td>Enable the Power Stage Controller 1 module.</td>
175 </tr>
176
177 <tr>
178 <td>power_psc1_disable()</td>
179 <td>Disable the Power Stage Controller 1 module.</td>
180 </tr>
181
182 <tr>
183 <td>power_psc2_enable()</td>
184 <td>Enable the Power Stage Controller 2 module.</td>
185 </tr>
186
187 <tr>
188 <td>power_psc2_disable()</td>
189 <td>Disable the Power Stage Controller 2 module.</td>
190 </tr>
191
192 <tr>
193 <td>power_ram0_enable()</td>
194 <td>Enable the SRAM block 0 .</td>
195 </tr>
196
197 <tr>
198 <td>power_ram0_disable()</td>
199 <td>Disable the SRAM block 0. </td>
200 </tr>
201
202 <tr>
203 <td>power_ram1_enable()</td>
204 <td>Enable the SRAM block 1 .</td>
205 </tr>
206
207 <tr>
208 <td>power_ram1_disable()</td>
209 <td>Disable the SRAM block 1. </td>
210 </tr>
211
212 <tr>
213 <td>power_ram2_enable()</td>
214 <td>Enable the SRAM block 2 .</td>
215 </tr>
216
217 <tr>
218 <td>power_ram2_disable()</td>
219 <td>Disable the SRAM block 2. </td>
220 </tr>
221
222 <tr>
223 <td>power_ram3_enable()</td>
224 <td>Enable the SRAM block 3 .</td>
225 </tr>
226
227 <tr>
228 <td>power_ram3_disable()</td>
229 <td>Disable the SRAM block 3. </td>
230 </tr>
231
232 <tr>
233 <td>power_rtc_disable()</td>
234 <td>Disable the RTC module</td>
235 </tr>
236
237 <tr>
238 <td>power_rtc_enable()</td>
239 <td>Enable the RTC module</td>
240 </tr>
241
242 <tr>
243 <td>power_spi_enable()</td>
244 <td>Enable the Serial Peripheral Interface module.</td>
245 </tr>
246
247 <tr>
248 <td>power_spi_disable()</td>
249 <td>Disable the Serial Peripheral Interface module.</td>
250 </tr>
251
252 <tr>
253 <td>power_spic_disable()</td>
254 <td>Disable the SPI module on PortC</td>
255 </tr>
256
257 <tr>
258 <td>power_spic_enable()</td>
259 <td>Enable the SPI module on PortC</td>
260 </tr>
261
262 <tr>
263 <td>power_spid_disable()</td>
264 <td>Disable the SPI module on PortD</td>
265 </tr>
266
267 <tr>
268 <td>power_spid_enable()</td>
269 <td>Enable the SPI module on PortD</td>
270 </tr>
271
272 <tr>
273 <td>power_tc0c_disable()</td>
274 <td>Disable the TC0 module on PortC</td>
275 </tr>
276
277 <tr>
278 <td>power_tc0c_enable()</td>
279 <td>Enable the TC0 module on PortC</td>
280 </tr>
281
282 <tr>
283 <td>power_tc0d_disable()</td>
284 <td>Disable the TC0 module on PortD</td>
285 </tr>
286
287 <tr>
288 <td>power_tc0d_enable()</td>
289 <td>Enable the TC0 module on PortD</td>
290 </tr>
291
292 <tr>
293 <td>power_tc0e_disable()</td>
294 <td>Disable the TC0 module on PortE</td>
295 </tr>
296
297 <tr>
298 <td>power_tc0e_enable()</td>
299 <td>Enable the TC0 module on PortE</td>
300 </tr>
301
302 <tr>
303 <td>power_tc0f_disable()</td>
304 <td>Disable the TC0 module on PortF</td>
305 </tr>
306
307 <tr>
308 <td>power_tc0f_enable()</td>
309 <td>Enable the TC0 module on PortF</td>
310 </tr>
311
312 <tr>
313 <td>power_tc1c_disable()</td>
314 <td>Disable the TC1 module on PortC</td>
315 </tr>
316
317 <tr>
318 <td>power_tc1c_enable()</td>
319 <td>Enable the TC1 module on PortC</td>
320 </tr>
321
322 <tr>
323 <td>power_twic_disable()</td>
324 <td>Disable the Two Wire Interface module on PortC</td>
325 </tr>
326
327 <tr>
328 <td>power_twic_enable()</td>
329 <td>Enable the Two Wire Interface module on PortC</td>
330 </tr>
331
332 <tr>
333 <td>power_twie_disable()</td>
334 <td>Disable the Two Wire Interface module on PortE</td>
335 </tr>
336
337 <tr>
338 <td>power_twie_enable()</td>
339 <td>Enable the Two Wire Interface module on PortE</td>
340 </tr>
341
342 <tr>
343 <td>power_timer0_enable()</td>
344 <td>Enable the Timer 0 module.</td>
345 </tr>
346
347 <tr>
348 <td>power_timer0_disable()</td>
349 <td>Disable the Timer 0 module.</td>
350 </tr>
351
352 <tr>
353 <td>power_timer1_enable()</td>
354 <td>Enable the Timer 1 module.</td>
355 </tr>
356
357 <tr>
358 <td>power_timer1_disable()</td>
359 <td>Disable the Timer 1 module.</td>
360 </tr>
361
362 <tr>
363 <td>power_timer2_enable()</td>
364 <td>Enable the Timer 2 module.</td>
365 </tr>
366
367 <tr>
368 <td>power_timer2_disable()</td>
369 <td>Disable the Timer 2 module.</td>
370 </tr>
371
372 <tr>
373 <td>power_timer3_enable()</td>
374 <td>Enable the Timer 3 module.</td>
375 </tr>
376
377 <tr>
378 <td>power_timer3_disable()</td>
379 <td>Disable the Timer 3 module.</td>
380 </tr>
381
382 <tr>
383 <td>power_timer4_enable()</td>
384 <td>Enable the Timer 4 module.</td>
385 </tr>
386
387 <tr>
388 <td>power_timer4_disable()</td>
389 <td>Disable the Timer 4 module.</td>
390 </tr>
391
392 <tr>
393 <td>power_timer5_enable()</td>
394 <td>Enable the Timer 5 module.</td>
395 </tr>
396
397 <tr>
398 <td>power_timer5_disable()</td>
399 <td>Disable the Timer 5 module.</td>
400 </tr>
401
402 <tr>
403 <td>power_twi_enable()</td>
404 <td>Enable the Two Wire Interface module.</td>
405 </tr>
406
407 <tr>
408 <td>power_twi_disable()</td>
409 <td>Disable the Two Wire Interface module.</td>
410 </tr>
411
412 <tr>
413 <td>power_usart_enable()</td>
414 <td>Enable the USART module.</td>
415 </tr>
416
417 <tr>
418 <td>power_usart_disable()</td>
419 <td>Disable the USART module.</td>
420 </tr>
421
422 <tr>
423 <td>power_usart0_enable()</td>
424 <td>Enable the USART 0 module.</td>
425 </tr>
426
427 <tr>
428 <td>power_usart0_disable()</td>
429 <td>Disable the USART 0 module.</td>
430 </tr>
431
432 <tr>
433 <td>power_usart1_enable()</td>
434 <td>Enable the USART 1 module.</td>
435 </tr>
436
437 <tr>
438 <td>power_usart1_disable()</td>
439 <td>Disable the USART 1 module.</td>
440 </tr>
441
442 <tr>
443 <td>power_usart2_enable()</td>
444 <td>Enable the USART 2 module.</td>
445 </tr>
446
447 <tr>
448 <td>power_usart2_disable()</td>
449 <td>Disable the USART 2 module.</td>
450 </tr>
451
452 <tr>
453 <td>power_usart3_enable()</td>
454 <td>Enable the USART 3 module.</td>
455 </tr>
456
457 <tr>
458 <td>power_usart3_disable()</td>
459 <td>Disable the USART 3 module.</td>
460 </tr>
461
462 <tr>
463 <td>power_usartc0_disable()</td>
464 <td> Disable the USART0 module on PortC</td>
465 </tr>
466
467 <tr>
468 <td>power_usartc0_enable()</td>
469 <td> Enable the USART0 module on PortC</td>
470 </tr>
471
472 <tr>
473 <td>power_usartd0_disable()</td>
474 <td> Disable the USART0 module on PortD</td>
475 </tr>
476
477 <tr>
478 <td>power_usartd0_enable()</td>
479 <td> Enable the USART0 module on PortD</td>
480 </tr>
481
482 <tr>
483 <td>power_usarte0_disable()</td>
484 <td> Disable the USART0 module on PortE</td>
485 </tr>
486
487 <tr>
488 <td>power_usarte0_enable()</td>
489 <td> Enable the USART0 module on PortE</td>
490 </tr>
491
492 <tr>
493 <td>power_usartf0_disable()</td>
494 <td> Disable the USART0 module on PortF</td>
495 </tr>
496
497 <tr>
498 <td>power_usartf0_enable()</td>
499 <td> Enable the USART0 module on PortF</td>
500 </tr>
501
502 <tr>
503 <td>power_usb_enable()</td>
504 <td>Enable the USB module.</td>
505 </tr>
506
507 <tr>
508 <td>power_usb_disable()</td>
509 <td>Disable the USB module.</td>
510 </tr>
511
512 <tr>
513 <td>power_usi_enable()</td>
514 <td>Enable the Universal Serial Interface module.</td>
515 </tr>
516
517 <tr>
518 <td>power_usi_disable()</td>
519 <td>Disable the Universal Serial Interface module.</td>
520 </tr>
521
522 <tr>
523 <td>power_vadc_enable()</td>
524 <td>Enable the Voltage ADC module.</td>
525 </tr>
526
527 <tr>
528 <td>power_vadc_disable()</td>
529 <td>Disable the Voltage ADC module.</td>
530 </tr>
531
532 <tr>
533 <td>power_all_enable()</td>
534 <td>Enable all modules.</td>
535 </tr>
536
537 <tr>
538 <td>power_all_disable()</td>
539 <td>Disable all modules.</td>
540 </tr>
541</table>
542</center>
543</small>
544
545@} */
546
547#if defined(__AVR_HAVE_PRR_PRADC)
548#define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
549#define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
550#endif
551
552#if defined(__AVR_HAVE_PRR_PRCAN)
553#define power_can_enable() (PRR &= (uint8_t)~(1 << PRCAN))
554#define power_can_disable() (PRR |= (uint8_t)(1 << PRCAN))
555#endif
556
557#if defined(__AVR_HAVE_PRR_PRLCD)
558#define power_lcd_enable() (PRR &= (uint8_t)~(1 << PRLCD))
559#define power_lcd_disable() (PRR |= (uint8_t)(1 << PRLCD))
560#endif
561
562#if defined(__AVR_HAVE_PRR_PRLIN)
563#define power_lin_enable() (PRR &= (uint8_t)~(1 << PRLIN))
564#define power_lin_disable() (PRR |= (uint8_t)(1 << PRLIN))
565#endif
566
567#if defined(__AVR_HAVE_PRR_PRPSC)
568#define power_psc_enable() (PRR &= (uint8_t)~(1 << PRPSC))
569#define power_psc_disable() (PRR |= (uint8_t)(1 << PRPSC))
570#endif
571
572#if defined(__AVR_HAVE_PRR_PRPSC0)
573#define power_psc0_enable() (PRR &= (uint8_t)~(1 << PRPSC0))
574#define power_psc0_disable() (PRR |= (uint8_t)(1 << PRPSC0))
575#endif
576
577#if defined(__AVR_HAVE_PRR_PRPSC1)
578#define power_psc1_enable() (PRR &= (uint8_t)~(1 << PRPSC1))
579#define power_psc1_disable() (PRR |= (uint8_t)(1 << PRPSC1))
580#endif
581
582#if defined(__AVR_HAVE_PRR_PRPSC2)
583#define power_psc2_enable() (PRR &= (uint8_t)~(1 << PRPSC2))
584#define power_psc2_disable() (PRR |= (uint8_t)(1 << PRPSC2))
585#endif
586
587#if defined(__AVR_HAVE_PRR_PRPSCR)
588#define power_pscr_enable() (PRR &= (uint8_t)~(1 << PRPSCR))
589#define power_pscr_disable() (PRR |= (uint8_t)(1 << PRPSCR))
590#endif
591
592#if defined(__AVR_HAVE_PRR_PRSPI)
593#define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI))
594#define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI))
595#endif
596
597#if defined(__AVR_HAVE_PRR_PRTIM0)
598#define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
599#define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
600#endif
601
602#if defined(__AVR_HAVE_PRR_PRTIM1)
603#define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1))
604#define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1))
605#endif
606
607#if defined(__AVR_HAVE_PRR_PRTIM2)
608#define power_timer2_enable() (PRR &= (uint8_t)~(1 << PRTIM2))
609#define power_timer2_disable() (PRR |= (uint8_t)(1 << PRTIM2))
610#endif
611
612#if defined(__AVR_HAVE_PRR_PRTWI)
613#define power_twi_enable() (PRR &= (uint8_t)~(1 << PRTWI))
614#define power_twi_disable() (PRR |= (uint8_t)(1 << PRTWI))
615#endif
616
617#if defined(__AVR_HAVE_PRR_PRUSART)
618#define power_usart_enable() (PRR &= (uint8_t)~(1 << PRUSART))
619#define power_usart_disable() (PRR |= (uint8_t)(1 << PRUSART))
620#endif
621
622#if defined(__AVR_HAVE_PRR_PRUSART0)
623#define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0))
624#define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0))
625#endif
626
627#if defined(__AVR_HAVE_PRR_PRUSART1)
628#define power_usart1_enable() (PRR &= (uint8_t)~(1 << PRUSART1))
629#define power_usart1_disable() (PRR |= (uint8_t)(1 << PRUSART1))
630#endif
631
632#if defined(__AVR_HAVE_PRR_PRUSI)
633#define power_usi_enable() (PRR &= (uint8_t)~(1 << PRUSI))
634#define power_usi_disable() (PRR |= (uint8_t)(1 << PRUSI))
635#endif
636
637#if defined(__AVR_HAVE_PRR0_PRADC)
638#define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
639#define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
640#endif
641
642#if defined(__AVR_HAVE_PRR0_PRC0)
643#define power_clock_output_enable() (PRR0 &= (uint8_t)~(1 << PRCO))
644#define power_clock_output_disable() (PRR0 |= (uint8_t)(1 << PRCO))
645#endif
646
647#if defined(__AVR_HAVE_PRR0_PRCRC)
648#define power_crc_enable() (PRR0 &= (uint8_t)~(1 << PRCRC))
649#define power_crc_disable() (PRR0 |= (uint8_t)(1 << PRCRC))
650#endif
651
652#if defined(__AVR_HAVE_PRR0_PRCU)
653#define power_crypto_enable() (PRR0 &= (uint8_t)~(1 << PRCU))
654#define power_crypto_disable() (PRR0 |= (uint8_t)(1 << PRCU))
655#endif
656
657#if defined(__AVR_HAVE_PRR0_PRDS)
658#define power_irdriver_enable() (PRR0 &= (uint8_t)~(1 << PRDS))
659#define power_irdriver_disable() (PRR0 |= (uint8_t)(1 << PRDS))
660#endif
661
662#if defined(__AVR_HAVE_PRR0_PRLFR)
663#define power_lfreceiver_enable() (PRR0 &= (uint8_t)~(1 << PRLFR))
664#define power_lfreceiver_disable() (PRR0 |= (uint8_t)(1 << PRLFR))
665#endif
666
667#if defined(__AVR_HAVE_PRR0_PRLFRS)
668#define power_lfrs_enable() (PRR0 &= (uint8_t)~(1 << PRLFRS))
669#define power_lfrs_disable() (PRR0 |= (uint8_t)(1 << PRLFRS))
670#endif
671
672#if defined(__AVR_HAVE_PRR0_PRLIN)
673#define power_lin_enable() (PRR0 &= (uint8_t)~(1 << PRLIN))
674#define power_lin_disable() (PRR0 |= (uint8_t)(1 << PRLIN))
675#endif
676
677#if defined(__AVR_HAVE_PRR0_PRPGA)
678#define power_pga_enable() (PRR0 &= (uint8_t)~(1 << PRPGA))
679#define power_pga_disable() (PRR0 |= (uint8_t)(1 << PRPGA))
680#endif
681
682#if defined(__AVR_HAVE_PRR0_PRRXDC)
683#define power_receive_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRRXDC))
684#define power_receive_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRRXDC))
685#endif
686
687#if defined(__AVR_HAVE_PRR0_PRSPI)
688#define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
689#define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
690#endif
691
692#if defined(__AVR_HAVE_PRR0_PRT0)
693#define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRT0))
694#define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRT0))
695#endif
696
697#if defined(__AVR_HAVE_PRR0_PRTIM0)
698#define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0))
699#define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
700#endif
701
702#if defined(__AVR_HAVE_PRR0_PRT1)
703#define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRT1))
704#define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRT1))
705#endif
706
707#if defined(__AVR_HAVE_PRR0_PRTIM1)
708#define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
709#define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
710#endif
711
712#if defined(__AVR_HAVE_PRR0_PRT2)
713#define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRT2))
714#define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRT2))
715#endif
716
717#if defined(__AVR_HAVE_PRR0_PRTIM2)
718#define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2))
719#define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2))
720#endif
721
722#if defined(__AVR_HAVE_PRR0_PRT3)
723#define power_timer3_enable() (PRR0 &= (uint8_t)~(1 << PRT3))
724#define power_timer3_disable() (PRR0 |= (uint8_t)(1 << PRT3))
725#endif
726
727#if defined(__AVR_HAVE_PRR0_PRTM)
728#define power_timermodulator_enable() (PRR0 &= (uint8_t)~(1 << PRTM))
729#define power_timermodulator_disable() (PRR0 |= (uint8_t)(1 << PRTM))
730#endif
731
732#if defined(__AVR_HAVE_PRR0_PRTWI)
733#define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
734#define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI))
735#endif
736
737#if defined(__AVR_HAVE_PRR0_PRTWI1)
738#define power_twi1_enable() (PRR0 &= (uint8_t)~(1 << PRTWI1))
739#define power_twi1_disable() (PRR0 |= (uint8_t)(1 << PRTWI1))
740#endif
741
742#if defined(__AVR_HAVE_PRR0_PRTXDC)
743#define power_transmit_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRTXDC))
744#define power_transmit_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRTXDC))
745#endif
746
747#if defined(__AVR_HAVE_PRR0_PRUSART0)
748#define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0))
749#define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0))
750#endif
751
752#if defined(__AVR_HAVE_PRR0_PRUSART1)
753#define power_usart1_enable() (PRR0 &= (uint8_t)~(1 << PRUSART1))
754#define power_usart1_disable() (PRR0 |= (uint8_t)(1 << PRUSART1))
755#endif
756
757#if defined(__AVR_HAVE_PRR0_PRVADC)
758#define power_vadc_enable() (PRR0 &= (uint8_t)~(1 << PRVADC))
759#define power_vadc_disable() (PRR0 |= (uint8_t)(1 << PRVADC))
760#endif
761
762#if defined(__AVR_HAVE_PRR0_PRVM)
763#define power_voltage_monitor_enable() (PRR0 &= (uint8_t)~(1 << PRVM))
764#define power_voltage_monitor_disable() (PRR0 |= (uint8_t)(1 << PRVM))
765#endif
766
767#if defined(__AVR_HAVE_PRR0_PRVRM)
768#define power_vrm_enable() (PRR0 &= (uint8_t)~(1 << PRVRM))
769#define power_vrm_disable() (PRR0 |= (uint8_t)(1 << PRVRM))
770#endif
771
772#if defined(__AVR_HAVE_PRR1_PRAES)
773#define power_aes_enable() (PRR1 &= (uint8_t)~(1 << PRAES))
774#define power_aes_disable() (PRR1 |= (uint8_t)(1 << PRAES))
775#endif
776
777#if defined(__AVR_HAVE_PRR1_PRCI)
778#define power_cinterface_enable() (PRR1 &= (uint8_t)~(1 << PRCI))
779#define power_cinterface_disable() (PRR1 |= (uint8_t)(1 << PRCI))
780#endif
781
782#if defined(__AVR_HAVE_PRR1_PRHSSPI)
783#define power_hsspi_enable() (PRR1 &= (uint8_t)~(1 << PRHSSPI))
784#define power_hsspi_disable() (PRR1 |= (uint8_t)(1 << PRHSSPI))
785#endif
786
787#if defined(__AVR_HAVE_PRR1_PRKB)
788#define power_kb_enable() (PRR1 &= (uint8_t)~(1 << PRKB))
789#define power_kb_disable() (PRR1 |= (uint8_t)(1 << PRKB))
790#endif
791
792#if defined(__AVR_HAVE_PRR1_PRLFPH)
793#define power_lfph_enable() (PRR1 &= (uint8_t)~(1 << PRLFPH))
794#define power_lfph_disable() (PRR1 |= (uint8_t)(1 << PRLFPH))
795#endif
796
797#if defined(__AVR_HAVE_PRR1_PRLFR)
798#define power_lfreceiver_enable() (PRR1 &= (uint8_t)~(1 << PRLFR))
799#define power_lfreceiver_disable() (PRR1 |= (uint8_t)(1 << PRLFR))
800#endif
801
802#if defined(__AVR_HAVE_PRR1_PRLFTP)
803#define power_lftp_enable() (PRR1 &= (uint8_t)~(1 << PRLFTP))
804#define power_lftp_disable() (PRR1 |= (uint8_t)(1 << PRLFTP))
805#endif
806
807#if defined(__AVR_HAVE_PRR1_PRSCI)
808#define power_sci_enable() (PRR1 &= (uint8_t)~(1 << PRSCI))
809#define power_sci_disable() (PRR1 |= (uint8_t)(1 << PRSCI))
810#endif
811
812#if defined(__AVR_HAVE_PRR1_PRSPI)
813#define power_spi_enable() (PRR1 &= (uint8_t)~(1 << PRSPI))
814#define power_spi_disable() (PRR1 |= (uint8_t)(1 << PRSPI))
815#endif
816
817#if defined(__AVR_HAVE_PRR1_PRT1)
818#define power_timer1_enable() (PRR1 &= (uint8_t)~(1 << PRT1))
819#define power_timer1_disable() (PRR1 |= (uint8_t)(1 << PRT1))
820#endif
821
822#if defined(__AVR_HAVE_PRR1_PRT2)
823#define power_timer2_enable() (PRR1 &= (uint8_t)~(1 << PRT2))
824#define power_timer2_disable() (PRR1 |= (uint8_t)(1 << PRT2))
825#endif
826
827#if defined(__AVR_HAVE_PRR1_PRT3)
828#define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRT3))
829#define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRT3))
830#endif
831
832#if defined(__AVR_HAVE_PRR1_PRT4)
833#define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRT4))
834#define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRT4))
835#endif
836
837#if defined(__AVR_HAVE_PRR1_PRT5)
838#define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRT5))
839#define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRT5))
840#endif
841
842#if defined(__AVR_HAVE_PRR1_PRTIM3)
843#define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3))
844#define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3))
845#endif
846
847#if defined(__AVR_HAVE_PRR1_PRTIM4)
848#define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRTIM4))
849#define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRTIM4))
850#endif
851
852#if defined(__AVR_HAVE_PRR1_PRTIM5)
853#define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRTIM5))
854#define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRTIM5))
855#endif
856
857#if defined(__AVR_HAVE_PRR1_PRTRX24)
858#define power_transceiver_enable() (PRR1 &= (uint8_t)~(1 << PRTRX24))
859#define power_transceiver_disable() (PRR1 |= (uint8_t)(1 << PRTRX24))
860#endif
861
862#if defined(__AVR_HAVE_PRR1_PRUSART1)
863#define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1))
864#define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1))
865#endif
866
867#if defined(__AVR_HAVE_PRR1_PRUSART2)
868#define power_usart2_enable() (PRR1 &= (uint8_t)~(1 << PRUSART2))
869#define power_usart2_disable() (PRR1 |= (uint8_t)(1 << PRUSART2))
870#endif
871
872#if defined(__AVR_HAVE_PRR1_PRUSART3)
873#define power_usart3_enable() (PRR1 &= (uint8_t)~(1 << PRUSART3))
874#define power_usart3_disable() (PRR1 |= (uint8_t)(1 << PRUSART3))
875#endif
876
877#if defined(__AVR_HAVE_PRR1_PRUSB)
878#define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB))
879#define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB))
880#endif
881
882#if defined(__AVR_HAVE_PRR1_PRUSBH)
883#define power_usbh_enable() (PRR1 &= (uint8_t)~(1 << PRUSBH))
884#define power_usbh_disable() (PRR1 |= (uint8_t)(1 << PRUSBH))
885#endif
886
887#if defined(__AVR_HAVE_PRR2_PRDF)
888#define power_data_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRDF))
889#define power_data_fifo_disable() (PRR2 |= (uint8_t)(1 << PRDF))
890#endif
891
892#if defined(__AVR_HAVE_PRR2_PRIDS)
893#define power_id_scan_enable() (PRR2 &= (uint8_t)~(1 << PRIDS))
894#define power_id_scan_disable() (PRR2 |= (uint8_t)(1 << PRIDS))
895#endif
896
897#if defined(__AVR_HAVE_PRR2_PRRAM0)
898#define power_ram0_enable() (PRR2 &= (uint8_t)~(1 << PRRAM0))
899#define power_ram0_disable() (PRR2 |= (uint8_t)(1 << PRRAM0))
900#endif
901
902#if defined(__AVR_HAVE_PRR2_PRRAM1)
903#define power_ram1_enable() (PRR2 &= (uint8_t)~(1 << PRRAM1))
904#define power_ram1_disable() (PRR2 |= (uint8_t)(1 << PRRAM1))
905#endif
906
907#if defined(__AVR_HAVE_PRR2_PRRAM2)
908#define power_ram2_enable() (PRR2 &= (uint8_t)~(1 << PRRAM2))
909#define power_ram2_disable() (PRR2 |= (uint8_t)(1 << PRRAM2))
910#endif
911
912#if defined(__AVR_HAVE_PRR2_PRRAM3)
913#define power_ram3_enable() (PRR2 &= (uint8_t)~(1 << PRRAM3))
914#define power_ram3_disable() (PRR2 |= (uint8_t)(1 << PRRAM3))
915#endif
916
917#if defined(__AVR_HAVE_PRR2_PRRS)
918#define power_rssi_buffer_enable() (PRR2 &= (uint8_t)~(1 << PRRS))
919#define power_rssi_buffer_disable() (PRR2 |= (uint8_t)(1 << PRRS))
920#endif
921
922#if defined(__AVR_HAVE_PRR2_PRSF)
923#define power_preamble_rssi_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRSF))
924#define power_preamble_rssi_fifo_disable() (PRR2 |= (uint8_t)(1 << PRSF))
925#endif
926
927#if defined(__AVR_HAVE_PRR2_PRSPI2)
928#define power_spi2_enable() (PRR2 &= (uint8_t)~(1 << PRSPI2))
929#define power_spi2_disable() (PRR2 |= (uint8_t)(1 << PRSPI2))
930#endif
931
932#if defined(__AVR_HAVE_PRR2_PRSSM)
933#define power_sequencer_state_machine_enable() (PRR2 &= (uint8_t)~(1 << PRSSM))
934#define power_sequencer_state_machine_disable() (PRR2 |= (uint8_t)(1 << PRSSM))
935#endif
936
937#if defined(__AVR_HAVE_PRR2_PRTM)
938#define power_tx_modulator_enable() (PRR2 &= (uint8_t)~(1 << PRTM))
939#define power_tx_modulator_disable() (PRR2 |= (uint8_t)(1 << PRTM))
940#endif
941
942#if defined(__AVR_HAVE_PRR2_PRTWI2)
943#define power_twi2_enable() (PRR2 &= (uint8_t)~(1 << PRTWI2))
944#define power_twi2_disable() (PRR2 |= (uint8_t)(1 << PRTWI2))
945#endif
946
947#if defined(__AVR_HAVE_PRR2_PRXA)
948#define power_rx_buffer_A_enable() (PRR2 &= (uint8_t)~(1 << PRXA))
949#define power_rx_buffer_A_disable() (PRR2 |= (uint8_t)(1 << PRXA))
950#endif
951
952#if defined(__AVR_HAVE_PRR2_PRXB)
953#define power_rx_buffer_B_enable() (PRR2 &= (uint8_t)~(1 << PRXB))
954#define power_rx_buffer_B_disable() (PRR2 |= (uint8_t)(1 << PRXB))
955#endif
956
957#if defined(__AVR_HAVE_PRGEN_AES)
958#define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm))
959#define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm)
960#endif
961
962#if defined(__AVR_HAVE_PRGEN_DMA)
963#define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm))
964#define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm)
965#endif
966
967#if defined(__AVR_HAVE_PRGEN_EBI)
968#define power_ebi_enable() (PR_PRGEN &= (uint8_t)~(PR_EBI_bm))
969#define power_ebi_disable() (PR_PRGEN |= (uint8_t)PR_EBI_bm)
970#endif
971
972#if defined(__AVR_HAVE_PRGEN_EDMA)
973#define power_edma_enable() (PR_PRGEN &= (uint8_t)~(PR_EDMA_bm))
974#define power_edma_disable() (PR_PRGEN |= (uint8_t)PR_EDMA_bm)
975#endif
976
977#if defined(__AVR_HAVE_PRGEN_EVSYS)
978#define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
979#define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
980#endif
981
982#if defined(__AVR_HAVE_PRGEN_LCD)
983#define power_lcd_enable() (PR_PRGEN &= (uint8_t)~(PR_LCD_bm))
984#define power_lcd_disable() (PR_PRGEN |= (uint8_t)PR_LCD_bm)
985#endif
986
987#if defined(__AVR_HAVE_PRGEN_RTC)
988#define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
989#define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
990#endif
991
992#if defined(__AVR_HAVE_PRGEN_USB)
993#define power_usb_enable() (PR_PRGEN &= (uint8_t)~(PR_USB_bm))
994#define power_usb_disable() (PR_PRGEN &= (uint8_t)(PR_USB_bm))
995#endif
996
997#if defined(__AVR_HAVE_PRGEN_XCL)
998#define power_xcl_enable() (PR_PRGEN &= (uint8_t)~(PR_XCL_bm))
999#define power_xcl_disable() (PR_PRGEN |= (uint8_t)PR_XCL_bm)
1000#endif
1001
1002#if defined(__AVR_HAVE_PRPA_AC)
1003#define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
1004#define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
1005#endif
1006
1007#if defined(__AVR_HAVE_PRPA_ADC)
1008#define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
1009#define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
1010#endif
1011
1012#if defined(__AVR_HAVE_PRPA_DAC)
1013#define power_daca_enable() (PR_PRPA &= (uint8_t)~(PR_DAC_bm))
1014#define power_daca_disable() (PR_PRPA |= (uint8_t)PR_DAC_bm)
1015#endif
1016
1017#if defined(__AVR_HAVE_PRPB_AC)
1018#define power_acb_enable() (PR_PRPB &= (uint8_t)~(PR_AC_bm))
1019#define power_acb_disable() (PR_PRPB |= (uint8_t)PR_AC_bm)
1020#endif
1021
1022#if defined(__AVR_HAVE_PRPB_ADC)
1023#define power_adcb_enable() (PR_PRPB &= (uint8_t)~(PR_ADC_bm))
1024#define power_adcb_disable() (PR_PRPB |= (uint8_t)PR_ADC_bm)
1025#endif
1026
1027#if defined(__AVR_HAVE_PRPB_DAC)
1028#define power_dacb_enable() (PR_PRPB &= (uint8_t)~(PR_DAC_bm))
1029#define power_dacb_disable() (PR_PRPB |= (uint8_t)PR_DAC_bm)
1030#endif
1031
1032#if defined(__AVR_HAVE_PRPC_HIRES)
1033#define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
1034#define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
1035#endif
1036
1037#if defined(__AVR_HAVE_PRPC_SPI)
1038#define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
1039#define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
1040#endif
1041
1042#if defined(__AVR_HAVE_PRPC_TC0)
1043#define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
1044#define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
1045#endif
1046
1047#if defined(__AVR_HAVE_PRPC_TC1)
1048#define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
1049#define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
1050#endif
1051
1052#if defined(__AVR_HAVE_PRPC_TC4)
1053#define power_tc4c_enable() (PR_PRPC &= (uint8_t)~(PR_TC4_bm))
1054#define power_tc4c_disable() (PR_PRPC |= (uint8_t)PR_TC4_bm)
1055#endif
1056
1057#if defined(__AVR_HAVE_PRPC_TC5)
1058#define power_tc5c_enable() (PR_PRPC &= (uint8_t)~(PR_TC5_bm))
1059#define power_tc5c_disable() (PR_PRPC |= (uint8_t)PR_TC5_bm)
1060#endif
1061
1062#if defined(__AVR_HAVE_PRPC_TWI)
1063#define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
1064#define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
1065#endif
1066
1067#if defined(__AVR_HAVE_PRPC_USART0)
1068#define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
1069#define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
1070#endif
1071
1072#if defined(__AVR_HAVE_PRPC_USART1)
1073#define power_usartc1_enable() (PR_PRPC &= (uint8_t)~(PR_USART1_bm))
1074#define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm)
1075#endif
1076
1077#if defined(__AVR_HAVE_PRPD_HIRES)
1078#define power_hiresd_enable() (PR_PRPD &= (uint8_t)~(PR_HIRES_bm))
1079#define power_hiresd_disable() (PR_PRPD |= (uint8_t)PR_HIRES_bm)
1080#endif
1081
1082#if defined(__AVR_HAVE_PRPD_SPI)
1083#define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
1084#define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm)
1085#endif
1086
1087#if defined(__AVR_HAVE_PRPD_TC0)
1088#define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
1089#define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm)
1090#endif
1091
1092#if defined(__AVR_HAVE_PRPD_TC1)
1093#define power_tc1d_enable() (PR_PRPD &= (uint8_t)~(PR_TC1_bm))
1094#define power_tc1d_disable() (PR_PRPD |= (uint8_t)PR_TC1_bm)
1095#endif
1096
1097#if defined(__AVR_HAVE_PRPD_TC5)
1098#define power_tc5d_enable() (PR_PRPD &= (uint8_t)~(PR_TC5_bm))
1099#define power_tc5d_disable() (PR_PRPD |= (uint8_t)PR_TC5_bm)
1100#endif
1101
1102#if defined(__AVR_HAVE_PRPD_TWI)
1103#define power_twid_enable() (PR_PRPD &= (uint8_t)~(PR_TWI_bm))
1104#define power_twid_disable() (PR_PRPD |= (uint8_t)PR_TWI_bm)
1105#endif
1106
1107#if defined(__AVR_HAVE_PRPD_USART0)
1108#define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
1109#define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
1110#endif
1111
1112#if defined(__AVR_HAVE_PRPD_USART1)
1113#define power_usartd1_enable() (PR_PRPD &= (uint8_t)~(PR_USART1_bm))
1114#define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm)
1115#endif
1116
1117#if defined(__AVR_HAVE_PRPE_HIRES)
1118#define power_hirese_enable() (PR_PRPE &= (uint8_t)~(PR_HIRES_bm))
1119#define power_hirese_disable() (PR_PRPE |= (uint8_t)PR_HIRES_bm)
1120#endif
1121
1122#if defined(__AVR_HAVE_PRPE_SPI)
1123#define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm))
1124#define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm)
1125#endif
1126
1127#if defined(__AVR_HAVE_PRPE_TC0)
1128#define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
1129#define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
1130#endif
1131
1132#if defined(__AVR_HAVE_PRPE_TC1)
1133#define power_tc1e_enable() (PR_PRPE &= (uint8_t)~(PR_TC1_bm))
1134#define power_tc1e_disable() (PR_PRPE |= (uint8_t)PR_TC1_bm)
1135#endif
1136
1137#if defined(__AVR_HAVE_PRPE_TWI)
1138#define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
1139#define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm)
1140#endif
1141
1142#if defined(__AVR_HAVE_PRPE_USART0)
1143#define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
1144#define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
1145#endif
1146
1147#if defined(__AVR_HAVE_PRPE_USART1)
1148#define power_usarte1_enable() (PR_PRPE &= (uint8_t)~(PR_USART1_bm))
1149#define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm)
1150#endif
1151
1152#if defined(__AVR_HAVE_PRPF_HIRES)
1153#define power_hiresf_enable() (PR_PRPF &= (uint8_t)~(PR_HIRES_bm))
1154#define power_hiresf_disable() (PR_PRPF |= (uint8_t)PR_HIRES_bm)
1155#endif
1156
1157#if defined(__AVR_HAVE_PRPF_SPI)
1158#define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm))
1159#define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm)
1160#endif
1161
1162#if defined(__AVR_HAVE_PRPF_TC0)
1163#define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
1164#define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
1165#endif
1166
1167#if defined(__AVR_HAVE_PRPF_TC1)
1168#define power_tc1f_enable() (PR_PRPF &= (uint8_t)~(PR_TC1_bm))
1169#define power_tc1f_disable() (PR_PRPF |= (uint8_t)PR_TC1_bm)
1170#endif
1171
1172#if defined(__AVR_HAVE_PRPF_TWI)
1173#define power_twif_enable() (PR_PRPF &= (uint8_t)~(PR_TWI_bm))
1174#define power_twif_disable() (PR_PRPF |= (uint8_t)PR_TWI_bm)
1175#endif
1176
1177#if defined(__AVR_HAVE_PRPF_USART0)
1178#define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
1179#define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
1180#endif
1181
1182#if defined(__AVR_HAVE_PRPF_USART1)
1183#define power_usartf1_enable() (PR_PRPF &= (uint8_t)~(PR_USART1_bm))
1184#define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm)
1185#endif
1186
1187static __inline void
1188__attribute__ ((__always_inline__))
1189__power_all_enable()
1190{
1191#ifdef __AVR_HAVE_PRR
1192 PRR &= (uint8_t)~(__AVR_HAVE_PRR);
1193#endif
1194
1195#ifdef __AVR_HAVE_PRR0
1196 PRR0 &= (uint8_t)~(__AVR_HAVE_PRR0);
1197#endif
1198
1199#ifdef __AVR_HAVE_PRR1
1200 PRR1 &= (uint8_t)~(__AVR_HAVE_PRR1);
1201#endif
1202
1203#ifdef __AVR_HAVE_PRR2
1204 PRR2 &= (uint8_t)~(__AVR_HAVE_PRR2);
1205#endif
1206
1207#ifdef __AVR_HAVE_PRGEN
1208 PR_PRGEN &= (uint8_t)~(__AVR_HAVE_PRGEN);
1209#endif
1210
1211#ifdef __AVR_HAVE_PRPA
1212 PR_PRPA &= (uint8_t)~(__AVR_HAVE_PRPA);
1213#endif
1214
1215#ifdef __AVR_HAVE_PRPB
1216 PR_PRPB &= (uint8_t)~(__AVR_HAVE_PRPB);
1217#endif
1218
1219#ifdef __AVR_HAVE_PRPC
1220 PR_PRPC &= (uint8_t)~(__AVR_HAVE_PRPC);
1221#endif
1222
1223#ifdef __AVR_HAVE_PRPD
1224 PR_PRPD &= (uint8_t)~(__AVR_HAVE_PRPD);
1225#endif
1226
1227#ifdef __AVR_HAVE_PRPE
1228 PR_PRPE &= (uint8_t)~(__AVR_HAVE_PRPE);
1229#endif
1230
1231#ifdef __AVR_HAVE_PRPF
1232 PR_PRPF &= (uint8_t)~(__AVR_HAVE_PRPF);
1233#endif
1234}
1235
1236static __inline void
1237 __attribute__ ((__always_inline__))
1238__power_all_disable()
1239{
1240#ifdef __AVR_HAVE_PRR
1241 PRR |= (uint8_t)(__AVR_HAVE_PRR);
1242#endif
1243
1244#ifdef __AVR_HAVE_PRR0
1245 PRR0 |= (uint8_t)(__AVR_HAVE_PRR0);
1246#endif
1247
1248#ifdef __AVR_HAVE_PRR1
1249 PRR1 |= (uint8_t)(__AVR_HAVE_PRR1);
1250#endif
1251
1252#ifdef __AVR_HAVE_PRR2
1253 PRR2 |= (uint8_t)(__AVR_HAVE_PRR2);
1254#endif
1255
1256#ifdef __AVR_HAVE_PRGEN
1257 PR_PRGEN |= (uint8_t)(__AVR_HAVE_PRGEN);
1258#endif
1259
1260#ifdef __AVR_HAVE_PRPA
1261 PR_PRPA |= (uint8_t)(__AVR_HAVE_PRPA);
1262#endif
1263
1264#ifdef __AVR_HAVE_PRPB
1265 PR_PRPB |= (uint8_t)(__AVR_HAVE_PRPB);
1266#endif
1267
1268#ifdef __AVR_HAVE_PRPC
1269 PR_PRPC |= (uint8_t)(__AVR_HAVE_PRPC);
1270#endif
1271
1272#ifdef __AVR_HAVE_PRPD
1273 PR_PRPD |= (uint8_t)(__AVR_HAVE_PRPD);
1274#endif
1275
1276#ifdef __AVR_HAVE_PRPE
1277 PR_PRPE |= (uint8_t)(__AVR_HAVE_PRPE);
1278#endif
1279
1280#ifdef __AVR_HAVE_PRPF
1281 PR_PRPF |= (uint8_t)(__AVR_HAVE_PRPF);
1282#endif
1283}
1284
1285#ifndef __DOXYGEN__
1286#ifndef power_all_enable
1287#define power_all_enable() __power_all_enable()
1288#endif
1289
1290#ifndef power_all_disable
1291#define power_all_disable() __power_all_disable()
1292#endif
1293#endif /* !__DOXYGEN__ */
1294
1295
1296#if defined(__AVR_AT90CAN32__) \
1297|| defined(__AVR_AT90CAN64__) \
1298|| defined(__AVR_AT90CAN128__) \
1299|| defined(__AVR_AT90PWM1__) \
1300|| defined(__AVR_AT90PWM2__) \
1301|| defined(__AVR_AT90PWM2B__) \
1302|| defined(__AVR_AT90PWM3__) \
1303|| defined(__AVR_AT90PWM3B__) \
1304|| defined(__AVR_AT90PWM81__) \
1305|| defined(__AVR_AT90PWM161__) \
1306|| defined(__AVR_AT90PWM216__) \
1307|| defined(__AVR_AT90PWM316__) \
1308|| defined(__AVR_AT90SCR100__) \
1309|| defined(__AVR_AT90USB646__) \
1310|| defined(__AVR_AT90USB647__) \
1311|| defined(__AVR_AT90USB82__) \
1312|| defined(__AVR_AT90USB1286__) \
1313|| defined(__AVR_AT90USB1287__) \
1314|| defined(__AVR_AT90USB162__) \
1315|| defined(__AVR_ATA5505__) \
1316|| defined(__AVR_ATA5272__) \
1317|| defined(__AVR_ATmega1280__) \
1318|| defined(__AVR_ATmega1281__) \
1319|| defined(__AVR_ATmega1284__) \
1320|| defined(__AVR_ATmega128RFA1__) \
1321|| defined(__AVR_ATmega1284RFR2__) \
1322|| defined(__AVR_ATmega128RFR2__) \
1323|| defined(__AVR_ATmega1284P__) \
1324|| defined(__AVR_ATmega162__) \
1325|| defined(__AVR_ATmega164A__) \
1326|| defined(__AVR_ATmega164P__) \
1327|| defined(__AVR_ATmega164PA__) \
1328|| defined(__AVR_ATmega165__) \
1329|| defined(__AVR_ATmega165A__) \
1330|| defined(__AVR_ATmega165P__) \
1331|| defined(__AVR_ATmega165PA__) \
1332|| defined(__AVR_ATmega168__) \
1333|| defined(__AVR_ATmega168P__) \
1334|| defined(__AVR_ATmega168PA__) \
1335|| defined(__AVR_ATmega169__) \
1336|| defined(__AVR_ATmega169A__) \
1337|| defined(__AVR_ATmega169P__) \
1338|| defined(__AVR_ATmega169PA__) \
1339|| defined(__AVR_ATmega16U4__) \
1340|| defined(__AVR_ATmega2560__) \
1341|| defined(__AVR_ATmega2561__) \
1342|| defined(__AVR_ATmega2564RFR2__) \
1343|| defined(__AVR_ATmega256RFR2__) \
1344|| defined(__AVR_ATmega324A__) \
1345|| defined(__AVR_ATmega324P__) \
1346|| defined(__AVR_ATmega324PA__) \
1347|| defined(__AVR_ATmega325__) \
1348|| defined(__AVR_ATmega325A__) \
1349|| defined(__AVR_ATmega325PA__) \
1350|| defined(__AVR_ATmega3250__) \
1351|| defined(__AVR_ATmega3250A__) \
1352|| defined(__AVR_ATmega3250PA__) \
1353|| defined(__AVR_ATmega328__) \
1354|| defined(__AVR_ATmega328P__) \
1355|| defined(__AVR_ATmega329__) \
1356|| defined(__AVR_ATmega329A__) \
1357|| defined(__AVR_ATmega329P__) \
1358|| defined(__AVR_ATmega329PA__) \
1359|| defined(__AVR_ATmega3290__) \
1360|| defined(__AVR_ATmega3290A__) \
1361|| defined(__AVR_ATmega3290PA__) \
1362|| defined(__AVR_ATmega32C1__) \
1363|| defined(__AVR_ATmega32M1__) \
1364|| defined(__AVR_ATmega32U2__) \
1365|| defined(__AVR_ATmega32U4__) \
1366|| defined(__AVR_ATmega32U6__) \
1367|| defined(__AVR_ATmega48__) \
1368|| defined(__AVR_ATmega48A__) \
1369|| defined(__AVR_ATmega48PA__) \
1370|| defined(__AVR_ATmega48P__) \
1371|| defined(__AVR_ATmega640__) \
1372|| defined(__AVR_ATmega649P__) \
1373|| defined(__AVR_ATmega644__) \
1374|| defined(__AVR_ATmega644A__) \
1375|| defined(__AVR_ATmega644P__) \
1376|| defined(__AVR_ATmega644PA__) \
1377|| defined(__AVR_ATmega645__) \
1378|| defined(__AVR_ATmega645A__) \
1379|| defined(__AVR_ATmega645P__) \
1380|| defined(__AVR_ATmega6450__) \
1381|| defined(__AVR_ATmega6450A__) \
1382|| defined(__AVR_ATmega6450P__) \
1383|| defined(__AVR_ATmega649__) \
1384|| defined(__AVR_ATmega649A__) \
1385|| defined(__AVR_ATmega6490__) \
1386|| defined(__AVR_ATmega6490A__) \
1387|| defined(__AVR_ATmega6490P__) \
1388|| defined(__AVR_ATmega644RFR2__) \
1389|| defined(__AVR_ATmega64RFR2__) \
1390|| defined(__AVR_ATmega88__) \
1391|| defined(__AVR_ATmega88P__) \
1392|| defined(__AVR_ATmega8U2__) \
1393|| defined(__AVR_ATmega16U2__) \
1394|| defined(__AVR_ATmega32U2__) \
1395|| defined(__AVR_ATtiny48__) \
1396|| defined(__AVR_ATtiny167__) \
1397|| defined(__DOXYGEN__)
1398
1399
1400/** \addtogroup avr_power
1401
1402Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that
1403allows you to decrease the system clock frequency and the power consumption
1404when the need for processing power is low.
1405On some earlier AVRs (ATmega103, ATmega64, ATmega128), similar
1406functionality can be achieved through the XTAL Divide Control Register.
1407Below are two macros and an enumerated type that can be used to
1408interface to the Clock Prescale Register or
1409XTAL Divide Control Register.
1410
1411\note Not all AVR devices have a clock prescaler. On those devices
1412without a Clock Prescale Register or XTAL Divide Control Register, these
1413macros are not available.
1414*/
1415
1416
1417/** \addtogroup avr_power
1418\code
1419typedef enum
1420{
1421 clock_div_1 = 0,
1422 clock_div_2 = 1,
1423 clock_div_4 = 2,
1424 clock_div_8 = 3,
1425 clock_div_16 = 4,
1426 clock_div_32 = 5,
1427 clock_div_64 = 6,
1428 clock_div_128 = 7,
1429 clock_div_256 = 8,
1430 clock_div_1_rc = 15, // ATmega128RFA1 only
1431} clock_div_t;
1432\endcode
1433Clock prescaler setting enumerations for device using
1434System Clock Prescale Register.
1435
1436\code
1437typedef enum
1438{
1439 clock_div_1 = 1,
1440 clock_div_2 = 2,
1441 clock_div_4 = 4,
1442 clock_div_8 = 8,
1443 clock_div_16 = 16,
1444 clock_div_32 = 32,
1445 clock_div_64 = 64,
1446 clock_div_128 = 128
1447} clock_div_t;
1448\endcode
1449Clock prescaler setting enumerations for device using
1450XTAL Divide Control Register.
1451
1452*/
1453#ifndef __DOXYGEN__
1454typedef enum
1455{
1456 clock_div_1 = 0,
1457 clock_div_2 = 1,
1458 clock_div_4 = 2,
1459 clock_div_8 = 3,
1460 clock_div_16 = 4,
1461 clock_div_32 = 5,
1462 clock_div_64 = 6,
1463 clock_div_128 = 7,
1464 clock_div_256 = 8
1465#if defined(__AVR_ATmega128RFA1__) \
1466|| defined(__AVR_ATmega2564RFR2__) \
1467|| defined(__AVR_ATmega1284RFR2__) \
1468|| defined(__AVR_ATmega644RFR2__) \
1469|| defined(__AVR_ATmega256RFR2__) \
1470|| defined(__AVR_ATmega128RFR2__) \
1471|| defined(__AVR_ATmega64RFR2__)
1472 , clock_div_1_rc = 15
1473#endif
1474} clock_div_t;
1475
1476static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1477#endif /* !__DOXYGEN__ */
1478
1479/**
1480 \ingroup avr_power
1481 \fn clock_prescale_set(clock_div_t x)
1482
1483Set the clock prescaler register select bits, selecting a system clock
1484division setting. This function is inlined, even if compiler
1485optimizations are disabled.
1486
1487The type of \c x is \c clock_div_t.
1488
1489\note For device with XTAL Divide Control Register (XDIV), \c x can actually range
1490from 1 to 129. Thus, one does not need to use \c clock_div_t type as argument.
1491*/
1492 void clock_prescale_set(clock_div_t __x)
1493{
1494 uint8_t __tmp = _BV(CLKPCE);
1495 __asm__ __volatile__ (
1496 "in __tmp_reg__,__SREG__" "\n\t"
1497 "cli" "\n\t"
1498 "sts %1, %0" "\n\t"
1499 "sts %1, %2" "\n\t"
1500 "out __SREG__, __tmp_reg__"
1501 : /* no outputs */
1502 : "d" (__tmp),
1503 "M" (_SFR_MEM_ADDR(CLKPR)),
1504 "d" (__x)
1505 : "r0");
1506}
1507
1508/** \addtogroup avr_power
1509\def clock_prescale_get()
1510Gets and returns the clock prescaler register setting. The return type is \c clock_div_t.
1511
1512\note For device with XTAL Divide Control Register (XDIV), return can actually
1513range from 1 to 129. Care should be taken has the return value could differ from the
1514typedef enum clock_div_t. This should only happen if clock_prescale_set was previously
1515called with a value other than those defined by \c clock_div_t.
1516*/
1517#define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1518
1519#elif defined(__AVR_ATmega16HVB__) \
1520|| defined(__AVR_ATmega16HVBREVB__) \
1521|| defined(__AVR_ATmega32HVB__) \
1522|| defined(__AVR_ATmega32HVBREVB__)
1523
1524typedef enum
1525{
1526 clock_div_1 = 0,
1527 clock_div_2 = 1,
1528 clock_div_4 = 2,
1529 clock_div_8 = 3
1530} clock_div_t;
1531
1532static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1533
1534void clock_prescale_set(clock_div_t __x)
1535{
1536 uint8_t __tmp = _BV(CLKPCE);
1537 __asm__ __volatile__ (
1538 "in __tmp_reg__,__SREG__" "\n\t"
1539 "cli" "\n\t"
1540 "sts %1, %0" "\n\t"
1541 "sts %1, %2" "\n\t"
1542 "out __SREG__, __tmp_reg__"
1543 : /* no outputs */
1544 : "d" (__tmp),
1545 "M" (_SFR_MEM_ADDR(CLKPR)),
1546 "d" (__x)
1547 : "r0");
1548}
1549
1550#define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)))
1551
1552#elif defined(__AVR_ATA5790__) \
1553|| defined (__AVR_ATA5795__)
1554
1555typedef enum
1556{
1557 clock_div_1 = 0,
1558 clock_div_2 = 1,
1559 clock_div_4 = 2,
1560 clock_div_8 = 3,
1561 clock_div_16 = 4,
1562 clock_div_32 = 5,
1563 clock_div_64 = 6,
1564 clock_div_128 = 7,
1565} clock_div_t;
1566
1567static __inline__ void system_clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1568
1569void system_clock_prescale_set(clock_div_t __x)
1570{
1571 uint8_t __tmp = _BV(CLKPCE);
1572 __asm__ __volatile__ (
1573 "in __tmp_reg__,__SREG__" "\n\t"
1574 "cli" "\n\t"
1575 "out %1, %0" "\n\t"
1576 "out %1, %2" "\n\t"
1577 "out __SREG__, __tmp_reg__"
1578 : /* no outputs */
1579 : "d" (__tmp),
1580 "I" (_SFR_IO_ADDR(CLKPR)),
1581 "d" (__x)
1582 : "r0");
1583}
1584
1585#define system_clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
1586
1587typedef enum
1588{
1589 timer_clock_div_reset = 0,
1590 timer_clock_div_1 = 1,
1591 timer_clock_div_2 = 2,
1592 timer_clock_div_4 = 3,
1593 timer_clock_div_8 = 4,
1594 timer_clock_div_16 = 5,
1595 timer_clock_div_32 = 6,
1596 timer_clock_div_64 = 7
1597} timer_clock_div_t;
1598
1599static __inline__ void timer_clock_prescale_set(timer_clock_div_t) __attribute__((__always_inline__));
1600
1601void timer_clock_prescale_set(timer_clock_div_t __x)
1602{
1603 uint8_t __t;
1604 __asm__ __volatile__ (
1605 "in __tmp_reg__,__SREG__" "\n\t"
1606 "cli" "\n\t"
1607 "in %[temp],%[clkpr]" "\n\t"
1608 "out %[clkpr],%[enable]" "\n\t"
1609 "andi %[temp],%[not_CLTPS]" "\n\t"
1610 "or %[temp], %[set_value]" "\n\t"
1611 "out %[clkpr],%[temp]" "\n\t"
1612 "sei" "\n\t"
1613 "out __SREG__,__tmp_reg__" "\n\t"
1614 : /* no outputs */
1615 : [temp] "r" (__t),
1616 [clkpr] "I" (_SFR_IO_ADDR(CLKPR)),
1617 [enable] "r" (_BV(CLKPCE)),
1618 [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
1619 [set_value] "r" ((__x & 7) << 3)
1620 : "r0");
1621}
1622
1623#define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
1624
1625#elif defined(__AVR_ATA6285__) \
1626|| defined(__AVR_ATA6286__)
1627
1628typedef enum
1629{
1630 clock_div_1 = 0,
1631 clock_div_2 = 1,
1632 clock_div_4 = 2,
1633 clock_div_8 = 3,
1634 clock_div_16 = 4,
1635 clock_div_32 = 5,
1636 clock_div_64 = 6,
1637 clock_div_128 = 7
1638} clock_div_t;
1639
1640static __inline__ void system_clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1641
1642void system_clock_prescale_set(clock_div_t __x)
1643{
1644 uint8_t __t;
1645 __asm__ __volatile__ (
1646 "in __tmp_reg__,__SREG__" "\n\t"
1647 "cli" "\n\t"
1648 "in %[temp],%[clpr]" "\n\t"
1649 "out %[clpr],%[enable]" "\n\t"
1650 "andi %[temp],%[not_CLKPS]" "\n\t"
1651 "or %[temp], %[set_value]" "\n\t"
1652 "out %[clpr],%[temp]" "\n\t"
1653 "sei" "\n\t"
1654 "out __SREG__,__tmp_reg__" "\n\t"
1655 : /* no outputs */
1656 : [temp] "r" (__t),
1657 [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
1658 [enable] "r" _BV(CLPCE),
1659 [not_CLKPS] "M" (0xFF & (~ ((1 << CLKPS2) | (1 << CLKPS1) | (1 << CLKPS0)))),
1660 [set_value] "r" (__x & 7)
1661 : "r0");
1662}
1663
1664#define system_clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
1665
1666typedef enum
1667{
1668 timer_clock_div_reset = 0,
1669 timer_clock_div_1 = 1,
1670 timer_clock_div_2 = 2,
1671 timer_clock_div_4 = 3,
1672 timer_clock_div_8 = 4,
1673 timer_clock_div_16 = 5,
1674 timer_clock_div_32 = 6,
1675 timer_clock_div_64 = 7
1676} timer_clock_div_t;
1677
1678static __inline__ void timer_clock_prescale_set(timer_clock_div_t) __attribute__((__always_inline__));
1679
1680void timer_clock_prescale_set(timer_clock_div_t __x)
1681{
1682 uint8_t __t;
1683 __asm__ __volatile__ (
1684 "in __tmp_reg__,__SREG__" "\n\t"
1685 "cli" "\n\t"
1686 "in %[temp],%[clpr]" "\n\t"
1687 "out %[clpr],%[enable]" "\n\t"
1688 "andi %[temp],%[not_CLTPS]" "\n\t"
1689 "or %[temp], %[set_value]" "\n\t"
1690 "out %[clpr],%[temp]" "\n\t"
1691 "sei" "\n\t"
1692 "out __SREG__,__tmp_reg__" "\n\t"
1693 : /* no outputs */
1694 : [temp] "r" (__t),
1695 [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
1696 [enable] "r" (_BV(CLPCE)),
1697 [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
1698 [set_value] "r" ((__x & 7) << 3)
1699 : "r0");
1700}
1701
1702#define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
1703
1704#elif defined(__AVR_ATtiny24__) \
1705|| defined(__AVR_ATtiny24A__) \
1706|| defined(__AVR_ATtiny44__) \
1707|| defined(__AVR_ATtiny44A__) \
1708|| defined(__AVR_ATtiny84__) \
1709|| defined(__AVR_ATtiny84A__) \
1710|| defined(__AVR_ATtiny25__) \
1711|| defined(__AVR_ATtiny45__) \
1712|| defined(__AVR_ATtiny85__) \
1713|| defined(__AVR_ATtiny261A__) \
1714|| defined(__AVR_ATtiny261__) \
1715|| defined(__AVR_ATtiny461__) \
1716|| defined(__AVR_ATtiny461A__) \
1717|| defined(__AVR_ATtiny861__) \
1718|| defined(__AVR_ATtiny861A__) \
1719|| defined(__AVR_ATtiny2313__) \
1720|| defined(__AVR_ATtiny2313A__) \
1721|| defined(__AVR_ATtiny4313__) \
1722|| defined(__AVR_ATtiny13__) \
1723|| defined(__AVR_ATtiny13A__) \
1724|| defined(__AVR_ATtiny43U__) \
1725
1726typedef enum
1727{
1728 clock_div_1 = 0,
1729 clock_div_2 = 1,
1730 clock_div_4 = 2,
1731 clock_div_8 = 3,
1732 clock_div_16 = 4,
1733 clock_div_32 = 5,
1734 clock_div_64 = 6,
1735 clock_div_128 = 7,
1736 clock_div_256 = 8
1737} clock_div_t;
1738
1739static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1740
1741void clock_prescale_set(clock_div_t __x)
1742{
1743 uint8_t __tmp = _BV(CLKPCE);
1744 __asm__ __volatile__ (
1745 "in __tmp_reg__,__SREG__" "\n\t"
1746 "cli" "\n\t"
1747 "out %1, %0" "\n\t"
1748 "out %1, %2" "\n\t"
1749 "out __SREG__, __tmp_reg__"
1750 : /* no outputs */
1751 : "d" (__tmp),
1752 "I" (_SFR_IO_ADDR(CLKPR)),
1753 "d" (__x)
1754 : "r0");
1755}
1756
1757
1758#define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1759
1760#elif defined(__AVR_ATmega64__) \
1761|| defined(__AVR_ATmega103__) \
1762|| defined(__AVR_ATmega128__)
1763
1764//Enum is declared for code compatibility
1765typedef enum
1766{
1767 clock_div_1 = 1,
1768 clock_div_2 = 2,
1769 clock_div_4 = 4,
1770 clock_div_8 = 8,
1771 clock_div_16 = 16,
1772 clock_div_32 = 32,
1773 clock_div_64 = 64,
1774 clock_div_128 = 128
1775} clock_div_t;
1776
1777static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1778
1779void clock_prescale_set(clock_div_t __x)
1780{
1781 if((__x <= 0) || (__x > 129))
1782 {
1783 return;//Invalid value.
1784 }
1785 else
1786 {
1787 uint8_t __tmp = 0;
1788 //Algo explained:
1789 //1 - Clear XDIV in order for it to accept a new value (actually only
1790 // XDIVEN need to be cleared, but clearing XDIV is faster than
1791 // read-modify-write since we will rewrite XDIV later anyway)
1792 //2 - wait 8 clock cycle for stability, see datasheet erreta
1793 //3 - Exist if requested prescaller is 1
1794 //4 - Calculate XDIV6..0 value = 129 - __x
1795 //5 - Set XDIVEN bit in calculated value
1796 //6 - write XDIV with calculated value
1797 //7 - wait 8 clock cycle for stability, see datasheet erreta
1798 __asm__ __volatile__ (
1799 "in __tmp_reg__,__SREG__" "\n\t"
1800 "cli" "\n\t"
1801 "out %1, __zero_reg__" "\n\t"
1802 "nop" "\n\t"
1803 "nop" "\n\t"
1804 "nop" "\n\t"
1805 "nop" "\n\t"
1806 "nop" "\n\t"
1807 "nop" "\n\t"
1808 "nop" "\n\t"
1809 "nop" "\n\t"
1810 "cpi %0, 0x01" "\n\t"
1811 "breq L_%=" "\n\t"
1812 "ldi %2, 0x81" "\n\t" //129
1813 "sub %2, %0" "\n\t"
1814 "ori %2, 0x80" "\n\t" //128
1815 "out %1, %2" "\n\t"
1816 "nop" "\n\t"
1817 "nop" "\n\t"
1818 "nop" "\n\t"
1819 "nop" "\n\t"
1820 "nop" "\n\t"
1821 "nop" "\n\t"
1822 "nop" "\n\t"
1823 "nop" "\n\t"
1824 "L_%=: " "out __SREG__, __tmp_reg__"
1825 : /* no outputs */
1826 :"d" (__x),
1827 "I" (_SFR_IO_ADDR(XDIV)),
1828 "d" (__tmp)
1829 : "r0");
1830 }
1831}
1832
1833static __inline__ clock_div_t clock_prescale_get(void) __attribute__((__always_inline__));
1834
1835clock_div_t clock_prescale_get(void)
1836{
1837 if(bit_is_clear(XDIV, XDIVEN))
1838 {
1839 return 1;
1840 }
1841 else
1842 {
1843 return (clock_div_t)(129 - (XDIV & 0x7F));
1844 }
1845}
1846
1847#elif defined(__AVR_ATtiny4__) \
1848|| defined(__AVR_ATtiny5__) \
1849|| defined(__AVR_ATtiny9__) \
1850|| defined(__AVR_ATtiny10__) \
1851|| defined(__AVR_ATtiny20__) \
1852|| defined(__AVR_ATtiny40__) \
1853
1854typedef enum
1855{
1856 clock_div_1 = 0,
1857 clock_div_2 = 1,
1858 clock_div_4 = 2,
1859 clock_div_8 = 3,
1860 clock_div_16 = 4,
1861 clock_div_32 = 5,
1862 clock_div_64 = 6,
1863 clock_div_128 = 7,
1864 clock_div_256 = 8
1865} clock_div_t;
1866
1867static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
1868
1869void clock_prescale_set(clock_div_t __x)
1870{
1871 uint8_t __tmp = 0xD8;
1872 __asm__ __volatile__ (
1873 "in __tmp_reg__,__SREG__" "\n\t"
1874 "cli" "\n\t"
1875 "out %1, %0" "\n\t"
1876 "out %2, %3" "\n\t"
1877 "out __SREG__, __tmp_reg__"
1878 : /* no outputs */
1879 : "d" (__tmp),
1880 "I" (_SFR_IO_ADDR(CCP)),
1881 "I" (_SFR_IO_ADDR(CLKPSR)),
1882 "d" (__x)
1883 : "r16");
1884}
1885
1886#define clock_prescale_get() (clock_div_t)(CLKPSR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
1887
1888#endif
1889
1890#endif /* _AVR_POWER_H_ */
clock_prescale_set
void clock_prescale_set(clock_div_t __x)
Definition: power.h:1492
_BV
#define _BV(bit)
Definition: sfr_defs.h:208
bit_is_clear
#define bit_is_clear(sfr, bit)
Definition: sfr_defs.h:245
uint8_t
unsigned char uint8_t
Definition: stdint.h:83
io.h
__attribute__
static __inline void __attribute__((__always_inline__)) __power_all_enable()
Definition: power.h:1188
clock_prescale_get
#define clock_prescale_get()
Definition: power.h:1517
stdint.h